The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
An integrated circuit (IC) such as a system on a chip (SoC) may include components to implement a plurality of features (for example only, a plurality of interfaces and/or protocols). Accordingly, processing components of the SoC (e.g., an application processor and/or embedded microcontroller) may be configured to support the plurality of features.
Referring now to FIG. 1, an example SoC 100 includes a plurality of peripheral feature interface modules 104-1, 104-2, 104-3, . . . , 104-n, referred to collectively as peripheral feature interface modules 104. The interface modules 104 may implement a plurality of features including, but not limited to, a universal serial bus (USB) interface, a universal asynchronous receiver/transmitter (UART) interface, a security support provider (SSP) interface, a secure digital input output (SDIO) interface, an I2C interface, and/or a serial peripheral interface. The interface modules 104 may each implement a different one of the features, or two or more of the interface modules 104 may implement the same feature (e.g., a first SSP interface and a second SSP interface, respectively).
The interface modules 104 provide an interface between a system bus 108 of the SoC 100 and one or more external input/output (I/O) ports 112. For example only, the system bus 108 may be an advanced high-performance bus (AHB), an advanced eXtensible interface (AXI) bus, another advanced microcontroller bus architecture (AMBA) bus, or any customized processor bus architecture. Each of the interface modules 104 may communicate independently with an associated I/O port 112, or one or more of the interface modules 104 may share a single I/O port 112 via a multiplexer 116 or other selector as shown.
The SoC 100 includes one or more processors 120-1, 120-2, . . . , and 120-m, referred to collectively as processors 120. For example only, the processor 120-1 may be a main processor (e.g., an ARM processor) and the processor 120-2 may be a digital signal processor (DSP). The processors 120 communicate with each other, the interface modules 104, and memory 124 via the system bus 108. The memory 124 may correspond to a plurality of memory modules including, for example only, various types of both volatile and non-volatile memory. The SoC 100 may include an external memory interface module 128 for interfacing with external memory (not shown). The SoC 100 may also include a wireless communication module 132 that provides wireless communication features for the SoC 100.
The SoC 100 includes a power supply module 136 and a clock management module 140. The power supply module 136 manages and provides power distribution to each of the interface modules 104. Conversely, the clock management module 140 provides one or more clock signals to each of the interface modules 104. Although the power supply module 136 and the clock management module 140 are only shown providing respective signals to the interface modules 104, it is to be understood that the power supply module 136 and the clock management module 140 also provide power distribution and clock signals, respectively, to other components of the SoC 100.
Referring now to FIG. 2, an example peripheral feature interface module 200 (e.g., that functions as a serial interface) communicates with the system bus 108 via a bus interface 204. The bus interface 204 provides an interface between the system bus 108 and registers 208 of the interface module 200 and/or a receiver first in first out (FIFO) buffer 212 and a transmitter FIFO buffer 216 of the interface module 200. For example only, the bus interface 204 may convert data received on the system bus 108 for data transactions with the transmitter FIFO buffer 216, and/or write operations on the registers 208. Conversely, the bus interface 204 may convert data received from the receiver FIFO buffer 212 and/or read from the registers 208 for data transactions on the system bus 108.
The interface module 200 includes a logic module 220 that implements control logic corresponding to the respective features of the interface module 200 (i.e., implements control logic corresponding to USB, UART, SSP, etc.). For example, the logic module 220 may include finite state machine (FSM) logic and/or glue logic. Accordingly, the logic module 220 communicates with the registers 208, the FIFO buffers 212 and 216, a receiver 224, and a transmitter 228 to provide specific functions associated with the corresponding interface module 200. For example, the FIFO buffers 212 and 216 provide data memory functions for the corresponding peripheral features. The receiver 224 and the transmitter 228 may convert parallel data of the FIFO buffers 212 and 216 to and from serial data of the I/O port 112. Each of the interface modules 104 as shown in FIG. 1 may implement each of the components of the interface module 200 as shown in FIG. 2.